The present invention relates in general to large-area, defect-tolerant VLSI integration such as, for example, LAI (large area integration) or WSI (wafer scale integration) which is beneficial for the integration of systems having an extremely high plurality of more than 10.sup.6 transistors. These systems can be designed with proven CMOS technology and have already reached orders of magnitude that will only be available with future submicron technology (in this respect, see the publication by Doctor Ramacher, "A Cost Oriented Redundancy Model for Defect-Tolerant VLSI/WSI Systems", Adam Hilger, Proc. of the Workshop on the Designing for Yield, January 1988). Configuration algorithms and configuration procedures have the function of locating a sub-set of function modules from a set of redundantly implemented function modules and to activate connections, so that a prescribed function (for example, an algorithm or a sequence of instructions) can be run on the configured set. One precondition for redundant implementations is that they can only be realized in systems whose architecture has a high degree of regularity. Systolic fields are extremely well suited for this purpose. An algorithm that allows mapping onto a two-dimensional, systolic field is a matrix-matrix multiplication, for example. Desirable for a large-area monolithic integration are:
(a) fault tolerance, i.e. effects appearing in the hardware realization of the configuration procedure do not prevent a configurability of the overall system;
(b) test compatibility, i.e., the system test needed for non-redundant design is used for the redundantly implemented system without additional hardware to detect the described defects and which activates a new configuration; and
(c) a minimum hardware requirement.
An article, "Wafer Scale Integration-Fault-Tolerant Procedure", by Aubusson and Catt, in IEEE J. Solid State, Volume SC-13, No. 3, June 1978, describes an effective algorithm for one-dimensional fields. Another publication by the authors J. H. Kim, S. M. Reddy, "On the Design of Easily Testable and Reconfigurable VLSI Processor Arrays", Workshop on Designing for Yield, Oxford 1987, disclose designs which meet the demands for (a) test compatibility, (b) defect tolerance and (c) minimum hardware to only an extremely limited extent. The publication, "Reconfiguration Architectures for VLSI Processing Arrays", Proc. of IEEE, May 1986, pages 712 through 722 by M. Sami and R. Steffanelli describes large-area monolithic integrations that do not at all meet the three demands of defect tolerance, test compatibility and minimum hardware requirement.
As a consequence of their regularity, systolic fields are extremely well-suited for a redundant system design. An effective configuration algorithm, but only for one-dimensional systolic fields, is disclosed in the aforementioned publication by Aubusson and Catt. However, a configuration procedure for two-dimensional, systolic fields that has the qualities of (a) defect tolerance (b) test compatibility and (c) minimum hardware requirement cannot be derived from this publication.